The working of modern electronic devices requires elaborate hardware architectures. Vulnerabilities in hardware are not just limited to security issues of software but are also seen in applications like automobiles, communication, medical systems, and satellites. Thus, it becomes very essential to detect these flaws even before the device is manufactured, and this is an integral part of hardware security verification.
There are some vulnerabilities that can only be identified with unusual inputs or under abnormal conditions. Discovering them early can help engineering teams mitigate security risks and prevent crippling post-silicon engineering changes.
Why Hardware Vulnerabilities Are Difficult to Detect
A hardware design could be working in a normal way and then subsequently fail in an unusual manner if the combination of inputs it receives is unusual. This can result in the possibility of access to sensitive registers in an unforeseen manner, exposing confidential data and/or executing hidden functionality.
Simulation-based Testing – evaluates the chosen scenarios. Though mandatory, it will not always be adequate for all combinations of inputs/sequences, especially in large RTL circuits.
This poses a problem for hardware security testing, because engineers don’t know how to find weaknesses that aren’t captured in normal testing.
Formal Verification in Hardware Security
Formal verification involves mathematical techniques to study the behavior of hardware in relation to specified properties and requirements. It does not just test a limited number of scenarios, but systematically tries a much wider variety of scenarios.
This practice enables engineers to detect unforeseen behavior, possible information leakage and uncommon trigger states prior to product manufacture.
Early detection becomes even more useful when it comes to correcting hardware vulnerabilities after they have been fabricated, which could result in significant redesign costs, delays in production and further validation.
The use of CWE to identify design weaknesses
The Common Weakness Enumeration (CWE) is a structured classification of known weaknesses in software, firmware and hardware developed by MITRE. The CWE categories make it easier for engineers to identify and understand common vulnerability patterns in hardware designs.
Siemens EDA has solutions for various parts of hardware security. These are Questa Verify Secure for information-flow verification, and Questa Verify Trust for structural weaknesses and suspicious design behaviour detection.
Questa Verify Trust analyzes RTL designs and identifies patterns related to possible security issues, according to the CWE-based checks.
Examples include:
- Unauthorized register access:Identifying design patterns that could potentially allow access to sensitive registers for unintended uses.
- Information exposure:Detecting the signal paths that can possibly leak protected information.
- Unexpected control behaviour:Indicating control logic that can behave in an unexpected way with unusual combinations of input.
This information can be used to explore possible weak points and understand that the design is working as expected.
Detecting Rare Triggers Before Chip Manufacturing
There may be some weaknesses or vulnerabilities in the hardware that don’t manifest until a very particular sequence of inputs is provided. This behaviour may be similar to a behaviour of a hardware Trojan in which the hidden or malicious function is activated only under specific circumstances.
Questa Verify Trust can be used to detect suspicious RTL structures and explore uncommon trigger conditions that are not addressed by traditional testing. When detected before fabrication, these problems enable design teams to discuss the logic, make revisions and validate the revised design.
Simulation, testing and other verification activities should not be a replacement for hardware security analysis, but should be used in conjunction with it.
Creating Hardware that is Trustworthy by Design
Building secure hardware is a process that needs to be addressed at all stages of the design process, and not only at the end before the product is tested. Formal verification in conjunction with CWE-based vulnerability analysis can help engineers to systematically explore potential vulnerabilities and help build confidence in their design.
Engineering teams can detect suspicious design patterns earlier with solutions like Questa Verify Trust and minimize exposure to designers’ hardware vulnerabilities and enable more secure electronic products.
Finally, the identification of the hidden weak points prior to manufacture of silicon makes hardware security a design consideration, not a post-manufacture issue.
Also Read: From Component Failure Rates to System Reliability: Connecting Reliability Prediction and RBD